Senior Design Verification Engineer – Coherent Interconnect
Job Description
Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC.
The collection of silicon proven interconnects, security IP, system controllers, debug and trace and IP tooling are all designed, validated and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Built upon the open AMBA interface standard, Arm System IP provides design teams with the foundation for building better systems.
The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points. Our group is seeking dedicated design verification engineers capable of completing our next generation of products.
Required Skills & Experience:
- Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science
- 4+ years of proven experience in verification/RTL design
- Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
- Experience with functional coverage verification methods.
- Excellent knowledge of scripting languages such as Python or Perl
'Nice to Have' Skills & Experience:
- Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
- Software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
- Experience in Formal Verification testbenches is a plus.
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