2027 Internship - Design Verification Engineer

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Cirrus Logic

Austin , Texas , United States
VHDL Verilog SystemVerilog UVM Digital Design HDL Verification
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For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

We are seeking highly motivated interns to join our Mixed-Signal Verification Engineering team to support the functional verification of industry-leading mixed-signal products. This internship offers a unique opportunity to work closely with digital and analog designers, applications engineers, and manufacturing test teams to ensure robust product performance through both pre-silicon verification and post-silicon validation.

We recruit interns year-round for Spring, Summer, and Fall 2027 opportunities. Each internship lasts 12–16 weeks and follows a full-time schedule.

Responsibilities
  • Assist in verification planning and strategy development.
  • Support testbench creation, maintenance, and enhancement.
  • Contribute to failure analysis, debug, and resolution efforts.
  • Help with coverage analysis and population to ensure thorough verification of mixed-signal products.
  • Work on digital/mixed-signal modeling, directed and constraint-random test generation, and verification flow development.
    • Required Skills and Qualifications
  • Currently pursuing a MS or PhD in Electrical Engineering or a related field.
  • Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL.
  • Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM, Vera, or e.
  • Solid understanding of digital design fundamentals and verification methodologies.

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