Mixed Signal Modelling and Verification Engineer (#GNEG4)

Cirrus Logic

Edinburgh , Scotland
Verilog SystemVerilog System Verilog UVM Verification
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For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

Cirrus Logic has an exciting opportunity for a talented Mixed signal, Modelling and Verification Engineer to join the Edinburgh or Newbury office. You will participate in all aspects of the verification process for complex mixed signal IC developments and contribute towards improvements in the mixed signal verification methodology within Cirrus Logic. This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation. In return, we offer you a great range of benefits including personal and professional development, a uniquely flat culture and much, much more!
Main Responsibilities:
  • Leadership of mixed signal verification activities, including resource planning, task assignment and reporting through to the delivery of thoroughly verified ICs.
  • Definition of IC verification strategy for complex mixed signal systems. Including modelling and selection of appropriate simulation techniques and environments.
  • Development of reliable and reusable mixed signal testbenches, compliant with industry standard verification techniques, for complex subsystems and mixed signal ICs. · Develop behavioural models using advanced modelling techniques including real number modelling, user-defined types and Verilog AMS.
  • Tool and methodology support for other Engineers working on mixed signal verification activities.
  • Hands-on project verification involvement, including testbench development, modelling of analog systems, netlisting and simulation.
  • Mentorship and support of other engineers to develop their skills and improve the verification practices within the team.
  • Collaboration with other Engineering disciplines to maximize efficiency of development activities.
    • Required Skills and Qualifications:
  • BEng / BSc / MEng / MSc Degree or equivalent in Electronics/Computer Science or other related discipline.
  • Proven track record in delivering 1st time success with complex mixed signal IC’s.
  • Experience of mixed signal simulation techniques and tools, including Spectre, AMS and Digital simulation.
  • Knowledge of SystemVerilog
  • Experience of analog and digital design.
  • Modelling of Analog subsystems using System Verilog and VerilogA/AMS.
  • Strong ability to interpret results and resolve problems.
  • Highly developed communication skills.
  • An innovative, creative, lateral thinking problem solver.
    • Preferred Skills and Qualifications:
  • Scripting experience with Python, sh/csh, TCL, Make
  • Object orientated programming (OOP) - Use of OOP design patterns
  • Knowledge of SVA (SystemVerilog Assertions)
  • Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification
  • Functional and code coverage analysis
  • Power aware verification (using CPF/UPF)
  • Testbench design with verification frameworks like UVM