Senior DFT Engineer

Cirrus Logic

Edinburgh , Scotland
Verilog SystemVerilog ASIC RTL STA DFT
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For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

We have an exciting opportunity for a talented DFT Engineer to join our growing team in Edinburgh. In this role, you will play a key role in defining and implementing robust DFT architectures across complex digital designs, enabling high manufacturing test coverage, silicon bring-up, and product reliability.

Responsibilities:
  • Define and implement chip-level and block-level DFT strategies for complex ASICs 
  • Develop and integrate scan architecture, compression logic, boundary scan, MBIST, and LBIST solutions 
  • Drive ATPG generation, fault simulation, diagnosis, and coverage closure 
  • Collaborate with RTL, verification, physical design, and test engineering teams 
  • Support synthesis, STA, and physical design flows with DFT based constraints 
  • Perform DFT verification using simulation 
  • Lead silicon bring-up, debug and failure diagnosis activities 
  • Develop automation scripts and methodologies to improve DFT productivity and quality 
    • Required Skills and Qualifications:
  • Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a DFT position
  • Strong understanding of digital design and test methodologies
  • Hands-on experience with: 
  • Scan insertion and scan compression
  • ATPG and fault simulation 
  • MBIST/LBIST implementation 
  • JTAG / IEEE 1149.1 standards 
  • Test coverage analysis and diagnosis. 
  • Experience with industry-standard EDA tools such as: 
  • Siemens Tessent 
  • Synopsys TetraMAX / TestMAX 
  • Strong scripting skills in Tcl & Python
  • Familiarity with Verilog/SystemVerilog and simulation environments 
  • Excellent debugging and problem-solving skills
  • Good communication and excellent collaboration skills.