Senior Digital Design Engineer (#OAEG3)

Cirrus Logic

Edinburgh , Scotland
Verilog SystemVerilog RTL UVM Place and Route DFT Verification
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For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

We have an exciting opportunity for a highly skilled Digital IC Design Engineer to join our growing design and development team in Edinburgh. You will work within our High-Performance Mixed-Signal R&D division, which develops industry-leading SoCs for global consumer markets. You will be part of an organisation operating at the forefront of cutting-edge technology.  
Key Responsibilities:
  • Design and develop new digital circuit architectures from concept, architecture, design, design integration through to production on advanced process nodes including development of block level testbenches  
  • Collaborate with a team of engineers with responsibility for the delivery of complex mixed-signal products and IPs   
  • Contribute to technical reviews and ensure IP quality using checklists  
  • Influence the growth of the team through supervision of junior engineers  
    • Required Skills and Qualifications:
  • Bachelor’s, Master's or Doctorate degree in Electrical Engineering (or related discipline) with an extensive proven background in digital CMOS circuit design  
  • Implementation of complex digital circuits and sub-systems in RTL using Verilog / SystemVerilog  
  • Understanding of digital system-level design, including use of standard bus protocols, bus architecture design and chip-level clock and reset architectures  
  • Verification of block-level digital designs   
  • Understanding of synthesis and timing analysis of digital circuits  
  • Good interpersonal skills, share technical expertise and knowledge, contribute to design reviews, work optimally to resolve conflicts  
  • Organised, detailed, and meticulous with strong communication skills  
  • Self-motivated with strong analytical and problem-solving skills  
  • Ability to work with a sense of urgency and thrive in a dynamic environment   
    • Preferred Skills and Qualifications:
  • An understanding, appreciation, and passion for mixed signal engineering   
  • Experience working within UVM based verification environments  
  • Scripting and automation of design tasks  
  • Experience with AMBA, SPI, I2C protocols   
  • Lab and silicon validation skills; Experience of chip bring-up and debug from design perspective  
  • Good understanding of Linting, CDC and RDC tools  
  • Collaboration with DFT and Place and Route teams  
  • Board level interface standards and interface design  
  • Experience with clock generation circuits and handling multiple clock domains  
  • Experience with Power gating and low power design techniques  
  • Experience with ARM, RISC-V, or similar microcontrollers as well as memory controllers  
  • DSP filter design using MATLAB and signal analysis techniques