Senior Formal Verification Engineer (CH-64001149)

Cirrus Logic logo

Cirrus Logic

Austin , Texas , United States
Verilog System Verilog UVM Digital Design Verification
Apply Now Posted July 30, 2026 Please mention FPGAjobs in your application — it helps a lot!
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

We are looking for an experienced Formal Verification Engineer to join our growing organization in Austin, TX! You will be a key member of a verification group striving to promote, develop, and support advanced formal verification techniques. In this role, you will be building and leveraging both formal and dynamic verification environments for critical areas of audio and mixed-signal devices, employing and supporting the usage of formal tools with design and verification teams.
Responsibilities:
  • Develop and enhance formal methodologies to be rolled out to the wider design and verification teams and investigate new capabilities based on formal.
  • Mentor engineers in formal verification, developing their talents and understanding of formal techniques and application of formal methodologies.
  • Support, and where necessary coach, the verification team to follow, and improve, defined methodology practices.
  • Develop test plans and verification methodologies to verify the microarchitecture and design.
  • Perform failure analysis and resolution, coverage analysis, and population.
  • Implement and improve functional verification.
    • Required Skills and Qualifications:
  • Master's degree in Electrical or Computer Engineering with 8+ years or PhD in Electrical or Computer Engineering with 5 +years of formal verification experience.
  • Proven expertise in designing and implementing formal verification environments for complex IP/module-level designs.
  • Demonstrated ability to lead and drive the verification process from inception to completion.
  • Excellent communication skills and a collaborative approach to working with team members.
  • Proficiency in System Verilog, UVM, or equivalent methodologies.
  • Familiarity with scripting languages such as Python, Perl, TCL, Bash.
  • Expertise in formal property languages, with SVA knowledge.
  • Experience in property-based model-checking.
  • Knowledgeable in Signal Processing, analog and digital design fundamentals.

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