Principal Engineer STA
Cortex Consultants LLC
Role Overview :
We are seeking a highly experienced Principal Engineer – STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology nodes.
Responsibilities :
Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs. Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios. Define timing constraints, validate SDCs, and ensure robust timing methodology execution. Timing closure for very low power designs. Anaylyze the timing closed SOC to reduce both dynamic and static power. Advise design team for any design changes which could meet timing requirements and still reduce power. Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence. Analyze and resolve complex timing violations and critical path bottlenecks. Support ECO implementation and signoff verification for advanced node tape-outs. Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements. Mentor engineers and lead technical reviews for timing architecture and signoff readiness.
Requirements :
10+ years of experience in STA and timing signoff for ASIC/SOC programs. Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. Strong expertise in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques. Hands-on experience with Synopsys PrimeTime, Tempus, StarRC, and related signoff tools. Strong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects. Experience with advanced technology nodes such as 7nm, 5nm, or below. Strong scripting skills in Tcl, Python, Perl, or Shell scripting. Excellent technical leadership, debugging, communication, and stakeholder management skills.
Good to Have :
Experience with package-aware timing analysis and chiplet architectures. Exposure to AI/ML-driven timing optimization methodologies.
Related openings
- Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus) — BAE Systems, San Diego, California, United States / Nashua, New Hampshire, United States / Austin, Texas, United States / Totowa, New Jersey, United States
- Design Verification Engineer — Broadcom, USA-CA San Jose Innovation Drive
- ASICS Design Verification Engineer — Qualcomm, San Diego, California, United States of America
- ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems — Qualcomm, San Diego, California, United States of America
- Staff FPGA Digital Design Engineer Level 5 (AHT) — Northrop Grumman, United States-California-Northridge
- System Performance Architect — Qualcomm, San Diego, California, United States of America