ASIC Verification Engineer

E-Space

Saratoga , California , United States
VHDL Verilog SystemVerilog FPGA ASIC RTL UVM HDL Verification
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Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

We are seeking a highly skilled and experienced Verification Engineer to join our engineering team. In this role, you will be responsible for designing, simulating, and verifying high-performance digital, analog and RF integrated circuits for applications such as 5G, IoT, and satellite communications. You will collaborate with cross-functional teams to define requirements, develop innovative design solutions, and ensure that products meet the highest standards of quality and performance.
What you will be doing:
  • Verify complex digital designs across custom IP blocks, subsystems, and full-chip SoC levels 
  • Translate architecture and micro-architecture specifications into executable verification plans 
  • Design, develop, and maintain scalable UVM-based verification environments 
  • Develop high-quality testbenches using SystemVerilog and support VHDL and mixed-language environments 
  • Drive functional and code coverage, analyze results, and close coverage gaps 
  • Debug complex issues using simulation, waveform analysis, assertions, and root-cause analysis 
  • Collaborate closely with architects, RTL designers, and system teams 
  • Document verification plans, methodologies, and results, and provide clear status updates to leadership
    • What you bring to this role:
  • Minimum of 5-10 years of experience in ASIC verification for complex digital systems 
  • Deep expertise in SystemVerilog and strong working knowledge of VHDL for design and verification in mixed-language environments 
  • Hands-on experience with UVM-based verification methodologies 
  • Solid understanding of digital design fundamentals 
  • Experience verifying industry-standard protocols  
  • Strong debugging skills using simulation tools and waveform analysis 
  • Excellent communication skills and ability to work effectively in cross-functional teams  
    • Bonus points for the following:
  • Advanced assertion-based verification or formal intent 
  • Exposure to gate-level simulation, formal verification, emulation, or FPGA prototyping 
  • Experience scaling or owning verification infrastructure for large or multi-project SoCs 
  • Experience in verifying complex SoCs integrating CPUs, DSPs, and mixed-signal blocks