Staff DV Engineer
E-Space
HDL & Verification Methodology
· Strong proficiency in Verilog and SystemVerilog
· Experience writing tests within an existing UVM verification environment
· Solid understanding of UVM architecture and methodology
Programming & Scripting
· Ability to write C/C++ code for verification purposes
· Some scripting experience in Perl or Python
Verification Planning & Execution
· Ability to contribute to and help write test plans
· Experience writing and maintaining verification tests
· Ability to debug RTL simulations independently
Leadership
· Experience leading design verification efforts at the block level
· Experience driving code coverage closure on assigned blocks
6+ years of design verification experience in the semiconductor industry
Hiring for this role?
Claim and feature it — priority homepage placement, your logo, and a slot in the jobs newsletter.
Claim and feature this jobRelated openings
- Staff Satellite FPGA Engineer (Digital Logic) — E-Space, Saratoga, CA,US
- Staff Satellite Electrical Engineer – Mixed Signal Circuits — E-Space, Saratoga, CA,US
- Staff FPGA Engineer (DSP) — E-Space, Saratoga, CA,US
- SoC Power Architecture Engineer - Processor Subsystem — E-Space, Saratoga, CA,US
- SoC Platform Engineer — E-Space, Saratoga, CA,US
- SoC Firmware Engineer — E-Space, Saratoga, CA,US