Principal Engineer - Synthesis & STA
Strong understanding of digital design principles, and experience with RTL coding in Verilog/System Verilog.
In your new role you will:
- Experience with power analysis and optimization flows such as power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling.
- Experience with scripting languages such as Perl, Python, or Tcl.
- Excellent problem-solving skills and ability to work independently andin a team environment.
- Strong communication and interpersonal skills, with the ability tointeract effectively with cross-functional teams.
- Proven track record of delivering successful designs on time and meeting performance, power, and area goals.
- Bachelors or Masters in Electrical/Electronics Engineering with 12+years of relevant experience.
- Strong understanding of digital design principles, and experience with RTL coding in Verilog/System Verilog.
- In-depth knowledge of synthesis methodologies and tools from leading EDA vendors.
- Experience with writing design constraints for synthesis, static timing analysis, timing closure, gate level simulation and pipelining at different levels for performance optimization and timing closure.