Senior CPU Physical Design Engineer
Intel
Haifa
, Haifa District
, Israel
RTL
STA
Place and Route
Synthesis
Verification
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Posted Aug. 13, 2026
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Job Details:
Job Description:
About the Team:
We created the Intel High Performance Processor (P-Core), a disruptive technology that enables a broad range of devices from entry PCs to high‑end servers. You will be part of a team participating in the design of a future‑generation high‑performance Intel microprocessor.
In this role you will:
- Design and deliver high‑performance CPU blocks from RTL to GDS, ready for manufacturing.
- Execute full physical design flow—including synthesis, floorplanning , place and route, CTS, timing closure, power/clock distribution, and reliability, power, and noise analysis.
- Lead verification and sign‑off (STA, equivalence, power integrity, LVS/DRC/ERC, and structural checks) to final convergence.
- Optimize designs for power, performance, and area using industry‑standard EDA tools (Cadence, Synopsys, Mentor, Ansys).
- Contribute to methodology and automation improvements.
- Mentor junior engineers.
Qualifications:
- B.Sc. or M.Sc. in Electrical or Computer Engineering, or equivalent.
- At least 10 years of experience in physical design using industry‑standard EDA tools – Using Cadence/Synopsys implementation tools.
Job Type:
Experienced HireShift:
Shift 1 (Israel)Primary Location:
Israel, HaifaAdditional Locations:
Israel, Petah-TikvaPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
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