Principal Engineer -Design

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

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Job Description:

Microchip’s Communications Business Unit (CBU) is a premier supplier of 100Gbps+ Optical Networking and Connectivity Solutions for Telecom and Hyperscale Data Center Networks. Our state-of-the-art devices power high-bandwidth, cloud-based applications including streaming services, social media platforms, and video conferencing worldwide.

The CBU Product Development team drives the full semiconductor R&D lifecycle—from initial concept, design, and implementation to embedded software integration, system validation lab testing, and mass-market production release. Working with the latest tools and methodologies in advanced process nodes, our experienced team delivers industry-leading network devices.

We are seeking a Principal Engineer to join the CBU Product Development team. In this role, you will lead the digital design, DFT, physical implementation, and static timing analysis (STA) of integrated circuits at both the block and top chip levels.

Working alongside our implementation team on advanced technology nodes, you will drive RTL-to-pre-layout netlist generation and own STA signoff across multiple macros, subsystems, and full-chip designs using industry-standard Cadence and Synopsys synthesis suites.

Requirements/Qualifications:

Qualification:

• Bachelor’s or Graduate Degree in: Computer Sciences, Electrical/Electronics/VLSI Engineering 

• 10 years of experience in synthesis, STA and Formal Verification with mainstream tools. 

• Excellent analytical and debugging skills and the ability to proactively solve issues 

• Strong coding skills and scripting skills (TCL, Perl or Python). 

• Proven ability to thrive on, learn and adapt to new methodologies and technologies 

• Hands on experience in RTL Design, synthesis, low-power logic insertion using UPF/CPF and STA signoff of Macro’s and SoC Level. 

• Good understanding of timing models, DFT, libs, hierarchical budgeting flows. 

• Hands-on to deliver solutions to critical design and execution issues related to synthesis. 

• Tapeout experience of 1 or more projects with 16nm or smaller silicon process technologies 

• Hands-on experience with synthesis tools like Cadence Genus OR Synopsys-DC/FC. 

• Good verbal and written communication skills in English, strong interpersonal skills 

Travel Time:

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