Senior Digital Verification Engineer

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Mythic AI

Bangalore , Indiana , United States
Verilog SystemVerilog RTL UVM Verification
Apply Now Posted July 28, 2026 Please mention FPGAjobs in your application — it helps a lot!
About us:
Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. The Mythic Analog Matrix Processor (Mythic AMP™) makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised a fresh round of funding, and has offices in Palo Alto, CA, and Austin, TX.
 
About the role:

At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended.

Because today’s AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches—combining simulation, modeling, and innovative verification strategies—to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.

Here is what you will do
  • Hands-on system-level and block-level verification.
  • Development of test plans and coverage plans.
  • Testbench development and execution using UVM or other advanced DV methodologies.
  • Creation of verification infrastructure and flows.
  • Leverage architecture models to help verify large AI network functionality on the design.
  • Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers.
    • Here's the background we hope you have:
  • Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering,.
  • 5+ years of industry experience developing verification testbenches.
  • Knowledge of verification methodologies (UVM or similar).
  • Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects.
  • Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems.
  • Understanding of Verilog, SystemVerilog, and UVM.
  • Knowledge of coverage-driven verification and advanced stimulus generation techniques.
  • Proven track record of first-pass silicon success.
  • Strong communication skills, both written and spoken.

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    The following would be nice to have, but is not required:
  • Exposure to formal verification methods and tools.
  • Familiarity with power-aware and performance-driven verification flows.
  • Prior experience verifying AI, DSP, or other highly parallel architectures.
  • Strong scripting skills (Python or similar) for automation and infrastructure development.

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