Senior Silicon Emulation Engineer

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Mythic AI

Austin , Texas , United States
Verilog SystemVerilog FPGA RTL Digital Design SOC Verification
Apply Now Posted July 28, 2026 Please mention FPGAjobs in your application — it helps a lot!
About us:

Mythic is building the future of AI computing with breakthrough analog  technology that delivers 100× the performance of traditional digital systems  at the same power and cost. This unlocks bigger, more capable models and  faster, more responsive applications—whether in edge devices like drones,  robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense.

We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.

Mythic's Digital Design Team is seeking a Silicon Emulation Engineer to support the development and validation of AI accelerator and AI-centric SoCs using hardware emulation platforms. This role is critical to enabling early bring-up, software validation, and performance analysis of neural network accelerators prior to silicon availability. The engineer will work closely with RTL, verification, compiler, firmware, and ML software teams to ensure functional correctness, performance targets, and system-level integration of AI workloads.
What You'll Do
  • Develop and maintain emulation platforms for AI accelerator / AI-centric SoCs
  • Integrate large-scale RTL (compute, DMA, memory subsystems, interconnects) into emulation environments
  • Enable early firmware, driver, runtime, and ML stack bring-up on emulated hardware
  • Support execution of AI inference workloads (e.g., CNNs, transformers) on emulated Mythic accelerators
  • Collaborate with compiler, runtime, and ML teams to debug HW/SW co-design issues
  • Develop scripts and automation for emulation builds, regressions, and workload execution
  • Analyze performance, bandwidth utilization, latency, and throughput of AI workloads in emulation
  • Debug complex issues spanning RTL, firmware, drivers, and user-space ML frameworks
  • Support post-silicon correlation and performance validation when applicable
  • Document emulation flows, performance methodologies, and debug procedures
    • What We're Looking For
  • Bachelor’s, Master's, or Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
  • Strong understanding of SoC architectures and AI accelerator design concepts
  • Experience with RTL simulation and emulation (Verilog/SystemVerilog)
  • Familiarity with hardware emulation platforms (e.g. Cadence Palladium)
  • Experience working in Linux-based environments
  • Proficiency in scripting (Python, Tcl, Bash)
  • Strong debugging skills across hardware and software layers
    • Nice to Have
  • Experience with NPU, DSP, or GPU-class accelerators
  • Experience running or debugging ML inference workloads on pre-silicon platforms
  • Knowledge of AI software stacks (runtime, compiler, graph execution)
  • Familiarity with DMA engines, memory hierarchies, and high-bandwidth interconnects
  • Understanding of AXI/AMBA protocols and cache coherency
  • Experience with FPGA prototyping or hybrid emulation flows
  • Exposure to performance modeling or architectural trade-off analysis

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