Digital Design Engineer Jobs

Principal FPGA Digital Design Engineer - Signing Bonus

BAE Systems Nashua, New Hampshire

VHDL Verilog

28d

Sr. Staff Engineer - Digital Design Verification

Ambiq Micro, Inc. Austin, Texas

Verilog SystemVerilog

28d

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

29d

Senior Staff Digital Design Engineer - Audio DSP Algorithm

Syntiant Bengaluru, Karnataka

Verilog System Verilog

29d

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

1mo

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

1mo

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

1mo

Digital Design Engineer

Northrop Grumman Rolling Meadows, Illinois

1mo

Electrical Engineer – Integrated Analog/Digital Design Level 3 /4

Northrop Grumman Sunnyvale, California

FPGA Digital Design

1mo

Principal Digital/Sr. Principal Digital Design Engineer

Northrop Grumman Rolling Meadows, Illinois

1mo

Principal/Sr. Principal Digital Design Engineer

Northrop Grumman Rolling Meadows, Illinois

1mo

Principal/Sr. Principal Digital Design Engineer

Northrop Grumman Rolling Meadows, Illinois

1mo

NVIDIA 2027 Internships: Digital Circuit Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

Associate Digital Design Engineer

Analog Devices San Jose, California

Verilog SystemVerilog

1mo

Digital Design Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

VHDL Verilog

1mo

Senior NVM Digital Designer

Mythic AI Palo Alto, California

Verilog SystemVerilog

1mo

Digital IC Design/Verification Engineer

Marvell Córdoba, Córdoba

VHDL Verilog

1mo

Digital IC Design Junior Engineer

Marvell Córdoba, Córdoba

VHDL Verilog

1mo

Senior Principal Digital IC Design Engineer

Marvell Santa Clara, California

Verilog SystemVerilog

1mo

Principal, IC Digital Design Engineer

Marvell Irvine, California

SystemVerilog FPGA

1mo