Principal Engineer - Hardware Sustaining

Job Description:

The Hardware Sustaining organization in HPE Networking Products and Technologies (NPAT) group has the primary responsibility of driving product hardware quality to ensure best-in-class customer experience. This position is for a Principal Engineer who will lead hardware failure analysis on HPE networking products. Must have a proven track record of driving root cause and corrective action activities on complex hardware, preferably in the networking domain. Must be a leader and subject matter expert who is able to scale impact through influence and mentoring of other team members and effective cross functional collaboration.

Responsibilities:

• Lead failure analysis of complex hardware problems requiring deep dive analysis into areas such as CPU, networking ASICs, power, clocking, high speed signals, optics, etc.

• Drive full range of corrective and preventive actions. This will include immediate containment or work-around options; determination and validation of final fix; identifying and addressing any other systems susceptible to the issue; and sharing lessons learned to avoid recurrence of similar issue in future products.

• Provide technical leadership in the Hardware Quality & Reliability domain. Guide and mentor junior team members.

• Collaborate with various Engineering, Manufacturing, ODM, and component / supply chain teams. Pull in the necessary subject matter experts to expedite problem remediation.

• Document findings and lessons learned. Provide regular failure analysis updates and final RCCA reports to internal stakeholders and customer support teams.

Education and Experience Required:

• Bachelor's or Master's degree in electrical engineering.

• 12+ years of experience (10+ years with Master's degree).

Knowledge and Skills:

• Expertise in hardware design processes and tools - schematic capture, layout, BoM, product life-cycle management (PLM) tools, etc.

• Expertise debugging Networking Hardware.

• Experience working with 20+ layer count boards featuring high speed (50G+) signals. Knowledge of signal integrity and power integrity concepts and tools.

• Expertise in design and debug of both high speed (PCIe, SerDes, DDR) and low speed (I2C, SPI) interfaces.

• Experience with FPGA and CPLD design and debug, Verilog RTL.

• Excellent written and verbal communication skills. Able to communicate effectively in English and local language.

• Excellent leadership skills. Demonstrated experience in a technical leader or subject matter expert role.

• Proficient in scripting for hardware design, test and debug.

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