FPGAjobs — Jobs for FPGA, ASIC and RTL engineers

Latest Posts

Post a Job Join Mailing List I want to be hired!

Aug. 17, 2026

Design/DSP/Verification Intern - PhD Degree

Marvell Santa Clara, California

SOC

1d

Physical Design Intern

Marvell Cordoba, Argentina

ASIC Static Timing

1d

Digital IC Design Intern

Marvell Cordoba, Argentina

RTL Digital Design

1d

Forward Error Correction Intern

Marvell Cordoba, Argentina

Verilog SystemVerilog

1d

Digital IC Design Intern

Marvell Cordoba, Argentina

VHDL Verilog

1d

Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)

Marvell Santa Clara, California

Verilog SystemVerilog

1d