Verilog Jobs in Santa Clara, CA

Browse open Verilog positions in Santa Clara, CA for FPGA, ASIC, and RTL engineers.

All Locations California 385 Texas 164 Austin, TX 154 Bangalore 138 Santa Clara, CA 132 San Diego, CA 77 Telangana 74 Hyderabad 74

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Power Management Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Cache Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Cache Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Power Management Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

Senior RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

CPU Power-Management Design Engineer

SiFive Multiple locations

Verilog SystemVerilog

1mo

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