34 open FPGA & RTL jobs at Silicon Labs
34 open logic design roles at Silicon Labs.
DFT jobs RTL jobs SOC jobs STA jobs SystemVerilog jobs UVM jobs Verification jobs Verilog jobs VHDL jobs Central Singapore Telangana Texas
Static Timing Analysis Engineer
Lead Engineer – IC Verification
Lead Engineer – RTL Design (Wireless Modem IP)
Chip Lead
Senior Design Verification Engineer
Senior Design Engineer
Digital Engineer
Design Verification Engineer II
Associate Staff Design Modeling Engineer
Design Engineer
2027 New College Graduates - Design Engineering
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