Oct. 14, 2026

Physical Design Intern - Master's Degree

Marvell Singapore, Central Singapore

ASIC RTL

22d

Design Verification- Intern

Marvell Petah-Tikva

Verilog System Verilog

22d

Oct. 13, 2026

System Software Engineering Intern, GPU and SOC - Summer 2027

NVIDIA Taipei, Taipei

SOC

23d

DFT Intern - 2027

NVIDIA Shanghai, Shanghai

Verilog Logic Design

23d

VLSI Logic Design Intern

HPE Juniper Networks Chippewa Falls, Wisconsin, United States of America

Verilog System Verilog

23d

ASIC Verification Engineering Intern

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

23d

VLSI Design Verification Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

VHDL Verilog

23d

VLSI Logic Design Intern

HPE Juniper Networks Ft. Collins, Colorado, United States of America

Verilog System Verilog

23d

ASIC Intern

HPE Juniper Networks Sunnyvale, California

VHDL Verilog

23d

Oct. 10, 2026

AI-Driven Physical Design Engineering (PhD Intern)

Intel Multiple locations

RTL Digital Design

26d

ASIC Engineer Intern

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

26d

Oct. 9, 2026

ASIC Verification/Design Engineering Intern

HPE Juniper Networks Roseville, California

Verilog ASIC

27d

Design Verification Intern

Marvell Da Nang, Đà Nẵng

Verilog SystemVerilog

27d

Oct. 8, 2026

ASIC Design Engineer Intern

HPE Juniper Networks Sunnyvale, California

ASIC RTL

28d

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

28d

2027 Electronic Engineering Internship

Cirrus Logic Edinburgh, Scotland

VHDL Verilog

28d

Oct. 7, 2026

PCIe Design Verification Intern - Summer 2027

NVIDIA Austin, Texas

SystemVerilog ASIC

29d

PCIe Design Verification Intern - Spring 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

29d

Hardware Engineering Intern

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

29d

Oct. 6, 2026

AI Compiler Formal Verification Intern

NVIDIA Multiple locations

Verification

1mo

Tools and Methodology Engineer, CAD DFT (RDSS Intern)

NVIDIA Multiple locations

Verilog DFT

1mo

Software Engineer – DFT CAD Tools (RDSS Intern)

NVIDIA Taipei, Taipei

Verilog ASIC

1mo

Intern - Next-Generation HBM Architecture

Micron Folsom, California

SystemVerilog RTL

1mo

2027 Internship - Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog RTL

1mo

2027 Internship - Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Oct. 5, 2026

Intern - Design Engineer, HBM

Micron Richardson, Texas

Verilog SOC

1mo

Digital IC Design- Intern

Marvell Yokneam

Logic Design Digital Design

1mo

Research Intern (PhD), FPGA & Silicon Prototyping

Marvell Hyderabad, Telangana

VHDL Verilog

1mo

Oct. 3, 2026

Internship Student Analog Mixed Signal verification F/M

NXP Semiconductors Catania, Sicily

Verification

1mo

ASIC Engineering Intern

HPE Juniper Networks Durham, North Carolina

ASIC Verification

1mo

Oct. 2, 2026

DFT Intern

Ambiq Micro, Inc. Singapore, Central Singapore

VHDL Verilog

1mo

Oct. 1, 2026

Integrated Circuits Intern (Summer 2027)

Draper Cambridge, Massachusetts

Verilog System Verilog

1mo

Sept. 30, 2026

DFT Engineer (RDSS Intern) - 2027

NVIDIA Multiple locations

RTL DFT

1mo

PhD Research Intern, AI Accelerator Design and VLSI - 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

1mo

AMS Verification Intern - Master's Degree

Marvell Singapore, Central Singapore

Verilog Verification

1mo

Sept. 29, 2026

Design Verification Engineer Intern

Micron Jalisco, Chiapas

Verilog SystemVerilog

1mo

Intern - ASIC Digital Design

Micron Minneapolis, Minnesota

ASIC Logic Design

1mo

Intern - Design Engineer, HBM

Micron Richardson, Texas

Verilog SOC

1mo

Intern – DRAM Technology Physical Design and Block-Level PPA Optimization

Micron Boise, Idaho

ASIC RTL

1mo

Intern Design Engineer - HIG HBM

Micron Richardson, Texas

VHDL Verilog

1mo

Intern - ASIC Validation

Micron Minneapolis, Minnesota

SystemVerilog ASIC

1mo

Intern – Memory Systems Architecture & AI

Micron San Jose, California

FPGA RTL

1mo

FY27 Intern - Soft IP ASIC Engineering Internship - Canada (12 or 16 months)

Qualcomm Ottawa, Ontario

VHDL Verilog

1mo

Sept. 25, 2026

Data Center Silicon Hardware Engineering Intern - BS - 2027 Co-Op

Marvell Multiple locations

Verilog SystemVerilog

1mo

Digital IC Design Engineering Intern

Semtech Burlington, Vermont

VHDL Verilog

1mo

Digital IC Design Engineering Intern

Semtech Ottawa, Ontario

VHDL Verilog

1mo

Sept. 24, 2026

EDT - FY27 Intern - Engineering Internship 2027 - 6 months, Cork

Qualcomm Cork, Munster

VHDL Verilog

1mo

Digital IC Design Intern

Marvell IL - Petah Tikva

RTL Logic Design

1mo

Security Verification/Validation Engineer Intern, BS - Summer 2027

Marvell Chandler, Arizona

Verilog System Verilog

1mo

Software Defined Radio Hardware Intern (Winter 2027)

Astranis San Francisco, California

FPGA Digital Design

1mo