STA Jobs in Santa Clara, CA

Physical Design Engineer, Timing

Tenstorrent Multiple locations

STA Static Timing

9m

Digital IC Design Intern, BS - Summer 2027

Marvell Multiple locations

Verilog ASIC

23h

Digital IC Design Intern, MS - Summer 2027

Marvell Multiple locations

Verilog ASIC

23h

RF/Analog Design/Mixed-Signal Engineering Internship – Summer 2027

Qualcomm Multiple locations

Verilog SystemVerilog

3d

Senior Staff Digital Design Engineer

Marvell Multiple locations

SystemVerilog FPGA

4d

Sr PD Engineer

Qualcomm Santa Clara, California

ASIC STA

5d

Physical Design and Timing Engineer Intern - Summer 2027

NVIDIA Santa Clara, California

RTL STA

5d

Physical Design CPU Methodology Engineer

Tenstorrent Santa Clara, California

ASIC RTL

12d

CPU Sever FV/CLP/STA engineer

Qualcomm Santa Clara, California

FPGA STA

12d

CPU SRAM Design & Layout Engineer

Qualcomm Santa Clara, California

Verilog Static Timing

12d

CPU Physical Electrical Analysis Engineer, Santa Clara/Austin

Qualcomm Santa Clara, California

STA Place and Route

14d

CPU Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

14d

Physical Design Engineer Intern, BS - Summer 2027

Marvell Multiple locations

ASIC RTL

17d

Physical Design Engineer Intern, MS - Summer 2027

Marvell Multiple locations

ASIC RTL

17d

Physical Design Engineer (Engineer up to Principal Level)

Qualcomm Multiple locations

ASIC RTL

20d

Design Automation Engineer - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

20d

Senior Static Timing Analysis (STA) Engineer

Intel Multiple locations

Logic Design Digital Design

20d

PD Engineer

Qualcomm Santa Clara, California

ASIC STA

21d

CPU Server Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

21d

CPU Server Physical Design Methodology, Infrastructure and Automation Engineer

Qualcomm Santa Clara, California

STA Place and Route

22d