Verilog Jobs

Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Principal Engineer - Hardware Sustaining

HPE Juniper Networks Singapore, Central Singapore

Verilog FPGA

1mo

Principal ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

ASIC Design Verification Engineer

HPE Juniper Networks Bengaluru, Karnataka

SystemVerilog ASIC

1mo

Design Verification Manager

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

Senior Design Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Principal Hardware Engineer

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

1mo

Sr. ASIC Design Engineer

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Director, ASIC Design & Front-End Implementation

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

1mo

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

FPGA Engineer

Belvedere Trading Chicago, Illinois

VHDL Verilog

1mo

FPGA Engineer

Headlands Technologies Multiple locations

VHDL Verilog

1mo

Senior FPGA Designer

Exegy Multiple locations

Remote VHDL Verilog

1mo

Principal Design Verification Engineer – CPU Coherent Interconnect

SiFive Multiple locations

SystemVerilog ASIC

1mo

Manager, DFT - Post Silicon

NVIDIA Tel Aviv, Tel Aviv District

Verilog RTL

1mo

Project Design Lead (EX)

Nexperia San Jose, California

Verilog SystemVerilog

1mo

Mixed Signal Design Verification (MSDV) Engineer

Nexperia Dallas, Texas

Verilog SystemVerilog

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo