SystemVerilog Jobs
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ASIC Design and Verification Intern, SOC - 2027
Sr. Staff Engineer, CPU (Front-End) Verification
Hardware Engineer (FPGA)
Neuromorphic Front-End Silicon Lead
ASIC Design Verification Engineer (Santa Clara, CA)
PhD Position (f/m/d) - Memory-Centric NPU Architectures and Emerging Memory Technologies for Edge AI
Engineer II, Physical Design - Cores
Staff Design Verification
Senior Design Verification Engineer
Senior Design Verification Engineer - FPGA
Sr. FPGA Design Engineer
Staff FPGA Engineer
Senior Staff Analog Mixed-Signal Design and Modelling Engineer
Senior FPGA Verification Engineer
Sr. Staff Engineer - Design Verification
Senior CPU Design Verification Engineer
Staff Formal Verification Engineer
Wireless R&D IP Verification Staff/Sr Staff Engineer
R&D Engineer, XR AI Software and Systems
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