SystemVerilog Jobs
Browse open SystemVerilog positions for FPGA, ASIC, and RTL engineers.
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197
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91
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86
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41
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34
ISP Design Engineer, up to Staff
CPU Emulation Sr Lead Engineer
Emulation Methodology Engineer
SoC Front-End Integrator, Senior to Staff (Hsinchu, Taipei)
High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei)
CPUSS Verification (Power Management), Staff/ Senior Staff
USB-Design Verification Senior Engineer
GPU Design Integration Engineer
Staff Engineer – Synthesized Model IP Design
Senior Verification Engineer / Lead Verification Engineer
Fundamental IP Design Kit and Characterization Manager
ASIC Engineering Director
Senior FPGA Verification Engineer, Air Dominance and Strike
Senior Digital Design Engineer, Air Dominance and Strike
CPU-Core RTL Director
Sensor Subsystem Design Engineer - Engineer OR Senior Level- Cork, Ireland
Director of Engineering for ML hardware design & Architecture
CPU RTL Methodology Engineer
Engineer
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