SystemVerilog Jobs in California
Browse open SystemVerilog positions in California for FPGA, ASIC, and RTL engineers.
All Locations
California
191
Texas
88
Austin, TX
83
Santa Clara, CA
63
Bangalore
56
Telangana
34
Hyderabad
34
San Diego, CA
33
Engineer ASIC
RF/Analog Design/Mixed-Signal Engineering Internship – Summer 2027
FE Engineering
Design Verification
Design Verification Engineer
Senior Staff Digital Design Engineer
Senior Methodologist for AIML Enhanced Design/Verification
Sr. Design Verification Engineer - Digital
Custom SOC IP Verification Engineer
Principal DFT Engineer
Midcore Design Verification Engineer
Front End Design Verification Engineer
Senior Principal ASIC Design Engineer
Senior FPGA Engineer
ASIC Design Verification Engineer (Santa Clara, CA)
Staff Design Verification Engineer – High Performance CPU Core
Staff Design Verification Engineer – CPU Core Verification (Vector)
Staff Design Verification Engineer – CPU Core Verification (ALU)
Senior Design Verification Engineer – High Performance CPU Core
Get notified about new SystemVerilog jobs
We'll email you when new SystemVerilog positions are posted.
Set up a job alert