UVM Jobs

Design Verification Engineer

Broadcom Multiple locations

SystemVerilog FPGA

1mo

R&D Engineer IC Design 5

Broadcom San Jose, California

Verilog SystemVerilog

1mo

ASIC VERIFICATION ENGINEER

Broadcom IND-Bangalore Electronic City - S1

SystemVerilog UVM

1mo

ASIC Verification Engineer

HPE Juniper Networks Roseville, California

SystemVerilog ASIC

1mo

Staff FPGA Design Engineer

Ursa Major Berthoud, Colorado

VHDL Verilog

1mo

Avionics Design Manager

Ursa Major Longmont, Colorado

SystemVerilog FPGA

1mo

Sr. FPGA Engineer II

Rocket Lab Long Beach, California

VHDL FPGA

1mo

Sr. FPGA Engineer I

Rocket Lab Long Beach, California

VHDL FPGA

1mo

FPGA Engineer II

Rocket Lab Long Beach, California

VHDL FPGA

1mo

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

SystemVerilog FPGA

1mo

Design Eng 2

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Hyderabad, Telangana

SystemVerilog FPGA

1mo

Principal Verification Engineer

Microchip Technology Dublin, Leinster

Verilog System Verilog

1mo

FPGA Verification Engineer II

Microchip Technology Dublin, Leinster

Verilog System Verilog

1mo

Principal Engineer, Design Verification Engineering

Analog Devices Dublin, Leinster

Verilog SystemVerilog

1mo

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

1mo

Principal AI Accelerator Architect Lead

Analog Devices Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer

Analog Devices Edinburgh, South Carolina

Verilog FPGA

1mo

Senior Engineer, Digital Design Engineering

Analog Devices Multiple locations

Verilog SystemVerilog

1mo