UVM Jobs

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Multiple locations

Verilog SystemVerilog

1mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

1mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

1mo

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic Multiple locations

FPGA ASIC

1mo

Staff Engineer, CPU Core Verification

Tenstorrent Bengaluru, Karnataka

RTL UVM

1mo

Sr Staff Engineer, SoC RTL Design

Tenstorrent Toronto, Ontario

VHDL Verilog

1mo

Sr. Engineer, SoC Design Verification

Tenstorrent Multiple locations

SystemVerilog RTL

1mo

Design Verification Lead, AI Hardware

Tenstorrent Toronto, Ontario

SystemVerilog FPGA

1mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

1mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

1mo

Manager/Director of Hardware Engineering

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Austin, Texas

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Cambridge, England

Verilog SystemVerilog

1mo

Hardware Verification Engineer

Baya Systems Santa Clara, California

Verilog SystemVerilog

1mo

Verification Engineer

Fractile London, England

Verilog SystemVerilog

1mo

Verification Engineer

Fractile Bristol

Verilog SystemVerilog

1mo

Senior Verification Engineer

Fractile London, England

Verilog SystemVerilog

1mo

Senior Verification Engineer

Fractile Bristol

Verilog SystemVerilog

1mo

Digital IC Design Engineer Intern

Neuralink South San Francisco, California, United States

SystemVerilog FPGA

1mo