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Senior Staff RTL Design Engineer - CPU Frontend

SiFive

Santa Clara , California , United States

VHDL Verilog System Verilog

Posted Aug. 5, 2026

Product Power Engineer

SiFive

Multiple Locations

FPGA ASIC RTL

Posted Aug. 5, 2026

Power Model Engineer

SiFive

Multiple Locations

FPGA ASIC RTL

Posted Aug. 5, 2026

Core Performance Architect

SiFive

Multiple Locations

FPGA RTL Verification

Posted Aug. 5, 2026

Core Performance Architect

SiFive

Multiple Locations

FPGA RTL Verification

Posted Aug. 5, 2026

Core Performance Architect

SiFive

Multiple Locations

FPGA RTL Verification

Posted Aug. 5, 2026

Senior FPGA Engineer (VHDL/Verilog)

AGAD Technology

Schelle, Flanders, Belgium

VHDL Verilog FPGA

Posted Aug. 4, 2026

ASIC Design and Integration Engineer – Silicon Security

Apple

Cupertino , California , United States

Verilog SystemVerilog ASIC

Posted Aug. 4, 2026

ASIC Design and Integration Engineer – Silicon Security

Apple

Cupertino , California , United States

ASIC RTL Synthesis

Posted Aug. 4, 2026

Summer 2027 Silicon Engineering Internship/Co-op

SpaceX

Flexible - Any SpaceX Site

VHDL Verilog ASIC

Posted Aug. 4, 2026

Sr. PCB Designer (Starlink)

SpaceX

Bastrop , Texas , United States

FPGA ASIC STA

Posted Aug. 4, 2026

Spring 2027 Silicon Engineering Internship/Co-op

SpaceX

Flexible - Any SpaceX Site

VHDL Verilog ASIC

Posted Aug. 4, 2026

Senior ASIC Emulation Engineer

K2 Space

United States - Remote

Verilog SystemVerilog FPGA

Posted Aug. 4, 2026

Senior ASIC Emulation Engineer

K2 Space

Seattle , Washington , United States

Verilog SystemVerilog FPGA

Posted Aug. 4, 2026

Hardware Engineer (FPGA/ASIC)

Jane Street

London , England , United Kingdom

VHDL Verilog FPGA

Posted Aug. 4, 2026

Hardware Engineer (FPGA/ASIC)

Jane Street

London , England , United Kingdom

VHDL Verilog FPGA

Posted Aug. 4, 2026

Intern - Design Verification Infrastructure Engineer - Platform

SiFive

Multiple Locations

Chisel Verification

Posted Aug. 2, 2026

CPU Processor Performance Verification Engineer

Apple

Santa Clara , California , United States

Verilog System Verilog RTL

Posted Aug. 1, 2026

CPU Processor Performance Verification Engineer

Apple

Santa Clara , California , United States

Verilog System Verilog RTL

Posted Aug. 1, 2026

CPU Processor Performance Verification Engineer

Apple

Santa Clara , California , United States

Verilog System Verilog RTL

Posted Aug. 1, 2026

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