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Electrical Design Engineer (Starshield)

SpaceX

Hawthorne , California , United States

FPGA ASIC STA

Posted Aug. 7, 2026

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Palo Alto , California , United States

Verilog SystemVerilog ASIC

Posted Aug. 7, 2026

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Austin , Texas , United States

Verilog SystemVerilog ASIC

Posted Aug. 7, 2026

Director- R&D Technical Head

Semtech

Hyderabad , Telangana , India

RTL DFT Verification

Posted Aug. 7, 2026

Staff SoC RTL Engineer

quadric, Inc

Burlingame , California , United States

Verilog SystemVerilog FPGA

Posted Aug. 7, 2026

Senior Design Verification Engineer

quadric, Inc

Pune , Maharashtra , India

Verilog SystemVerilog ASIC

Posted Aug. 7, 2026

Sr. Reliability/Verification Engineer

Ouster

San Francisco , California , United States

Posted Aug. 7, 2026

Technical Program Manager, Silicon

Anthropic

Multiple Locations

ASIC RTL DFT

Posted Aug. 7, 2026

Staff RTL Design Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

VHDL Verilog System Verilog

Posted Aug. 6, 2026

Electrical Design Engineer, Satellites Payload (Starlink)

SpaceX

Palo Alto , California , United States

FPGA ASIC STA

Posted Aug. 6, 2026

Digital Verification Engineer

Neuralink

South San Francisco, California, United States

Verilog SystemVerilog FPGA

Posted Aug. 5, 2026

Staff System Validation Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

FPGA Chisel Verification

Posted Aug. 5, 2026

Staff Design Verification Engineer – Cache Verification

SiFive

Hsinchu , Hsinchu , Taiwan

Verilog SystemVerilog FPGA

Posted Aug. 5, 2026

Staff Design Verification Engineer – Cache Verification

SiFive

Hsinchu , Hsinchu , Taiwan

Verilog SystemVerilog FPGA

Posted Aug. 5, 2026

Senior Design Verification Engineer – Cache Verification

SiFive

Hsinchu , Hsinchu , Taiwan

Verilog SystemVerilog FPGA

Posted Aug. 5, 2026

Senior Design Verification Engineer – High Performance CPU Core

SiFive

Multiple Locations

Verilog SystemVerilog RTL

Posted Aug. 5, 2026

Senior Design Verification Engineer – High Performance CPU Core

SiFive

Multiple Locations

Verilog SystemVerilog RTL

Posted Aug. 5, 2026

Staff Design Verification Engineer – High Performance CPU Core

SiFive

Multiple Locations

Verilog SystemVerilog ASIC

Posted Aug. 5, 2026

Staff Design Verification Engineer – High Performance CPU Core

SiFive

Multiple Locations

Verilog SystemVerilog ASIC

Posted Aug. 5, 2026

Staff Design Verification Engineer – High Performance CPU Core

SiFive

Multiple Locations

Verilog SystemVerilog ASIC

Posted Aug. 5, 2026

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