July 28, 2026

Senior Engineer, FPGA

Ambiq Micro, Inc. Singapore, Central Singapore

Verilog System Verilog

2mo

Senior Embedded Graphics Software Engineer

Ambiq Micro, Inc. Singapore, Central Singapore

FPGA SOC

2mo

Senior Director - System Architecture

Ambiq Micro, Inc. Austin, Texas

FPGA RTL

2mo

Principal SoC RTL Engineer

Ambiq Micro, Inc. Austin, Texas

Verilog SystemVerilog

2mo

Memory Design Engineer

Ambiq Micro, Inc. Singapore, Central Singapore

STA DFT

2mo

Embedded Software Engineer - Security

Ambiq Micro, Inc. Austin, Texas

FPGA SOC

2mo

Physical Design Engineer

Cerebras Systems Sunnyvale, California

RTL STA

2mo

Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

2mo

Senior Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

2mo

Senior Engineer: Post Silicon - Bring Up

Cerebras Systems Bengaluru, Karnataka

Verilog System Verilog

2mo

Principal AI Accelerator Architect

Cerebras Systems Sunnyvale, California

RTL Synthesis

2mo

Lead RTL Design Engineer

Cerebras Systems Sunnyvale, California

FPGA ASIC

2mo

Sr. Staff / Principal Firmware Engineer - Flash Interface Layer (FIL)

SK hynix memory solutions America Inc. San Jose, California

FPGA ASIC

2mo

July 25, 2026

Hardware Engineer (FPGA/ASIC)

Jane Street New York City, New York

VHDL Verilog

2mo

Security Analyst (SOC)

SpaceX Hawthorne, California

SOC

2mo

July 24, 2026

Principal Engineer, SOC Integration

Samsung Semiconductor San Jose, California

ASIC Static Timing

2mo

July 23, 2026

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

2mo

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

2mo

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

2mo

Sr. SI/PI Engineer - Serdes, Satellites (Starlink)

SpaceX Palo Alto, California

FPGA ASIC

2mo

Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink)

SpaceX Palo Alto, California

FPGA ASIC

2mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

2mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

Verilog System Verilog

2mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

Verilog System Verilog

2mo

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX Irvine, California

Verilog System Verilog

2mo

Sr. PCB Designer

SpaceX Hawthorne, California

FPGA Digital Design

2mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Sunnyvale, California

ASIC DFT

2mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC DFT

2mo

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC DFT

2mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Irvine, California

ASIC DFT

2mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Palo Alto, California

ASIC DFT

2mo

Sr. ASIC DFT Engineer (Silicon)

SpaceX Austin, Texas

ASIC DFT

2mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

2mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

2mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

ASIC RTL

2mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

2mo

Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, California

Verilog System Verilog

2mo

Sr. Antenna Engineer (Starship)

SpaceX Hawthorne, California

FPGA HLS

2mo

July 22, 2026

RTL Design Engineer (Silicon Engineering)

SpaceX Irvine, California

VHDL Verilog

2mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

FPGA ASIC

2mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

FPGA ASIC

2mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

FPGA ASIC

2mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

FPGA ASIC

2mo

Principal ASIC Design Engineer (Starshield)

SpaceX Hawthorne, California

Verilog System Verilog

2mo

PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

2mo

Manager, ASIC Design Engineering (Starshield Silicon)

SpaceX Hawthorne, California

Verilog System Verilog

2mo

Lead PCB Designer (Starshield)

SpaceX Hawthorne, California

FPGA Digital Design

2mo

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

VHDL Verilog

2mo

EDA Engineer (RFIC Engineering)

SpaceX Irvine, California

Digital Design STA

2mo

EDA Engineer (RFIC Engineering)

SpaceX Redmond, Washington

Digital Design STA

2mo