FPGAjobs - Jobs for Logic Designers!

Latest Posts

Post a Job Join Mailing List I want to be hired!

Staff RTL Design Engineer - CPU LS/PF/MMU

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Staff Engineer - Design Verification

SiFive

Hyderabad , Telangana , India

Verilog SystemVerilog UVM

Posted July 28, 2026

Senior Staff Verification Engineer For Worldguard

SiFive

Bengaluru , Karnataka , India

Verilog SystemVerilog System Verilog

Posted July 28, 2026

Senior IP Verification Engineer(IOMMU-N)

SiFive

Bengaluru , Karnataka , India

Verilog System Verilog RTL

Posted July 28, 2026

Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive

Multiple Locations

Verilog SystemVerilog FPGA

Posted July 28, 2026

Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive

Multiple Locations

Verilog SystemVerilog FPGA

Posted July 28, 2026

Principal Interconnect Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Interconnect Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Engineer I

SiFive

Bengaluru , Karnataka , India

VHDL Verilog System Verilog

Posted July 28, 2026

Sr. Staff Hardware Design Engineer

SiFive

La Ciotat , Provence-Alpes-Côte-d’Azur , France

Verilog SystemVerilog RTL

Posted July 28, 2026

Senior / Staff Design Verification Engineer

SiFive

Ahmedabad , Gujarat , India

Verilog SystemVerilog System Verilog

Posted July 28, 2026

Staff Engineer, Physical Design

SiFive

Bengaluru , Karnataka , India

RTL STA Static Timing

Posted July 28, 2026

CPU Design Verification Engineer

SiFive

Hyderabad , Telangana , India

Verilog System Verilog RTL

Posted July 28, 2026

Senior Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive

Bengaluru , Karnataka , India

Verilog System Verilog UVM

Posted July 28, 2026

Interconnect Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Design Verification Engineer to Staff Engineer (Unit Level Test)

SiFive

Hsinchu , Hsinchu , Taiwan

Verilog SystemVerilog UVM

Posted July 28, 2026

Principal Design Verification Engineer – CPU Core LSU

SiFive

Multiple Locations

RTL Verification

Posted July 28, 2026

Principal Design Verification Engineer – CPU Subsystem Power Management

SiFive

Multiple Locations

Verilog SystemVerilog ASIC

Posted July 28, 2026

Principal Design Verification Engineer – CPU Core Hardware Prefetch

SiFive

Multiple Locations

RTL Verification

Posted July 28, 2026

Principal Design Verification Engineer – CPU Core Frontend

SiFive

Multiple Locations

RTL Verification

Posted July 28, 2026

Show me more