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Staff Verification Engineer

SiFive

Multiple Locations

Verification

Posted July 28, 2026

System Validation Engineer to Staff Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

FPGA Chisel Verification

Posted July 28, 2026

RTL Design Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

VHDL Verilog System Verilog

Posted July 28, 2026

Senior Verification Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

Verilog SystemVerilog FPGA

Posted July 28, 2026

Staff Design Verification Engineer – Coherent Interconnect

SiFive

Multiple Locations

Verilog SystemVerilog FPGA

Posted July 28, 2026

Principal Design Verification Engineer – High Performance CPU Subsystem

SiFive

Multiple Locations

RTL Verification

Posted July 28, 2026

Staff Engineer, Low Power Verification & Formal Equivalence

SiFive

Bengaluru , Karnataka , India

ASIC RTL Verification

Posted July 28, 2026

Staff Design Verification Engineer – Coherent Interconnect

SiFive

Multiple Locations

Verilog SystemVerilog FPGA

Posted July 28, 2026

Intern - Design Verification Infrastructure Engineer - Platform

SiFive

Multiple Locations

Chisel Verification

Posted July 28, 2026

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive

Bengaluru , Karnataka , India

Verilog System Verilog UVM

Posted July 28, 2026

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

SiFive

Bengaluru , Karnataka , India

Verilog System Verilog UVM

Posted July 28, 2026

Staff Design Verification Engineer

SiFive

Hsinchu , Hsinchu , Taiwan

Verification

Posted July 28, 2026

Senior ALU Design Engineer

SiFive

Cambridge , England , United Kingdom

VHDL Verilog System Verilog

Posted July 28, 2026

Lead Debug/Trace/Profiling Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Debug/Trace/Profiling Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Staff Engineer - Formal Verification

SiFive

Bengaluru , Karnataka , India

VHDL Verilog SystemVerilog

Posted July 28, 2026

Staff Engineer

SiFive

Ahmedabad , Gujarat , India

Verilog SystemVerilog FPGA

Posted July 28, 2026

Interconnect Design Engineer

SiFive

Multiple Locations

VHDL Verilog System Verilog

Posted July 28, 2026

Staff Engineer - DV

SiFive

Bengaluru , Karnataka , India

Verilog System Verilog UVM

Posted July 28, 2026

Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

SiFive

Hyderabad , Telangana , India

Verilog System Verilog ASIC

Posted July 28, 2026

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