SystemVerilog Jobs in Santa Clara, CA
Browse open SystemVerilog positions in Santa Clara, CA for FPGA, ASIC, and RTL engineers.
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70
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Staff Design Verification Engineer – High Performance CPU Core
Staff Design Verification Engineer – High Performance CPU Core
Staff Design Verification Engineer – High Performance CPU Core
CPU Power-Management Design Engineer
Principal Design Verification Engineer – CPU Subsystem Power Management
Sr. Engineer, SoC Design Verification
CPU Verification Fellow, RISC-V High-Performance Processor
Manager/Director of Hardware Engineering
Hardware Verification Engineer
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