SystemVerilog Jobs in Santa Clara, CA
Browse open SystemVerilog positions in Santa Clara, CA for FPGA, ASIC, and RTL engineers.
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California
205
Texas
106
Austin, TX
91
Santa Clara, CA
70
Bangalore
60
Telangana
44
Hyderabad
44
Ontario
35
Senior Staff Formal Verification Engineer
Sr. Staff Engineer, CPU (Front-End) Verification
Neuromorphic Front-End Silicon Lead
ASIC Design Verification Engineer (Santa Clara, CA)
CPU-Core RTL Director
CPU RTL Methodology Engineer
Power Management IC Design
Staff Engineer - Power Management IC Design
CPU Emulation Engineer
Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development
Design Verification Engineer — Memory Subsystem
CPU RTL/AI Micro-Architect - AI Development
Sr. Engineer, SoC Design Verification Engineer, System Management Controller
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