Sept. 4, 2026

Data Center SoC Power & Limits Architect

Qualcomm Multiple locations

ASIC SOC

12d

Senior HW Program Manager

Qualcomm Bangalore, India

RTL Synthesis

12d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

12d

RISCV CPU System RTL Engineer

Qualcomm Multiple locations

VHDL Verilog

12d

CPU System and Compute Die Architect

Qualcomm Multiple locations

RTL Logic Design

12d

Power Integrity Design Engineer – PDN / EMIR - Cork, Ireland

Qualcomm Cork, Munster

ASIC RTL

12d

Yield Diagnostics Engineer, up to staff

Qualcomm Hsinchu City, Taiwan

ASIC Digital Design

12d

Lead CPU Firmware Verification and Validation Engineer/ Manager

Qualcomm Santa Clara, California

DFT Design for Test

12d

Senior SoC Performance Architect

Qualcomm Multiple locations

SOC

12d

ASIC Validation Engineer

Qualcomm Pune, Maharashtra

FPGA RTL

12d

Staff Machine Learning Engineer – Automotive Cybersecurity

Qualcomm San Diego, California

RTL SOC

12d

ASIC Design Verification Engineer, up to Sr. Staff

Qualcomm Hsinchu City, Taiwan

Verilog System Verilog

12d

Linux Platform & HLOS Stack Developer, Senior/Staff - Cork, Ireland

Qualcomm Cork, Munster

ASIC SOC

12d

Validation Engineer, Senior

Qualcomm Toronto, Ontario

ASIC SOC

12d

Manager Embedded Software Engineer 2

Northrop Grumman San Diego, California

VHDL Verilog

12d

Principal FPGA/Firmware Engineer

CACI Colorado Springs, Colorado

VHDL Verilog

12d

PhD Position (f/m/d) - Memory-Centric NPU Architectures and Emerging Memory Technologies for Edge AI

NXP Semiconductors Hamburg, Hamburg

VHDL Verilog

12d

DfT Architect

NXP Semiconductors Multiple locations

RTL DFT

12d

Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture

SiFive Bengaluru, Karnataka

RTL

12d

Senior Engineer, Physical Design - Interconnects

SiFive Bengaluru, Karnataka

RTL Place and Route

12d

Engineer II, Physical Design - Cores

SiFive Bengaluru, Karnataka

Verilog SystemVerilog

12d

Staff Engineer CPU DV

SiFive Hyderabad, Telangana

Verilog System Verilog

12d

Staff - Formal Verification Engineer

SiFive Bengaluru, Karnataka

VHDL Verilog

12d

Staff Design Verification

SiFive Hyderabad, Telangana

SystemVerilog ASIC

12d

Senior Design Verification Engineer

SiFive Hyderabad, Telangana

Verilog SystemVerilog

12d

Sr Engineer, Low Power Verification & Formal Equivalence

SiFive Bengaluru, Karnataka

ASIC RTL

12d

Senior FPGA Design Engineer

BAE Systems Multiple locations

VHDL Verilog

12d

Senior Principal FPGA Design Engineer

BAE Systems Manchester, New Hampshire

VHDL Verilog

12d

Senior Design Verification Engineer - FPGA

BAE Systems Multiple locations

VHDL SystemVerilog

12d

Principal IC Analog / Mixed Signal Design Engineer

Analog Devices Wilmington, Massachusetts

DFT SOC

12d

FPGA Engineer I

CesiumAstro Austin, Texas

VHDL Verilog

12d

Sr. FPGA Design Engineer

A2e Technologies San Diego, California

VHDL SystemVerilog

12d

Sr. Director, SoC Architecture

Ambiq Micro, Inc. Austin, Texas

FPGA SOC

12d

TOP Design Verification Engineer Intern

SK hynix memory solutions America Inc. San Jose, California

Verilog System Verilog

12d

Principal Engineer, SOC Design

Samsung Semiconductor San Jose, California

ASIC RTL

12d

Sept. 3, 2026

Staff FPGA Engineer

IonQ Oxford, England

VHDL Verilog

12d

Staff Electrical Hardware Design Engineer

IonQ Multiple locations

FPGA Digital Design

12d

Staff Electrical Engineer- Testing

IonQ Pleasanton, California

FPGA DFT

12d

Senior Staff Analog Mixed-Signal Design and Modelling Engineer

IonQ Oxford, England

Verilog SystemVerilog

12d

Senior Staff Electrical Engineer

IonQ Multiple locations

FPGA Digital Design

12d

Senior FPGA Verification Engineer

IonQ Oxford, England

SystemVerilog FPGA

12d

Senior Electrical Engineer - Space

IonQ Pleasanton, California

FPGA RTL

12d

Senior Electrical Engineer

IonQ Pleasanton, California

FPGA ASIC

12d

Associate Firmware Engineer

IonQ Pleasanton, California

FPGA ASIC

12d

Silicon Hardware Engineering - Intern, Graduate

Intel Multiple locations

Logic Design DFT

13d

Silicon Hardware Engineering - Intern, Bachelor’s

Intel Multiple locations

Logic Design DFT

13d

Principal Digital Engineer or Sr. Principal Digital Engineer (SkillBridge)

Northrop Grumman Baltimore, Maryland

VHDL FPGA

13d

Sr. Staff Engineer - Design Verification

SiFive Hyderabad, Telangana

Verilog SystemVerilog

13d

Senior CPU Design Verification Engineer

SiFive Hyderabad, Telangana

Verilog SystemVerilog

13d

Staff Design Verification Engineer

SiFive Hyderabad, Telangana

Verilog System Verilog

13d