July 31, 2026

Principal Design Validation & Test (DVT) Engineer

Celero Communications, Inc. Irvine, California

ASIC RTL

1mo

July 30, 2026

System Emulation and Evaluation Engineer

Cirrus Logic Edinburgh, Scotland

FPGA ASIC

1mo

Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Staff Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Senior Staff Post Silicon Validation Engineer - Global Operations

Cirrus Logic Austin, Texas

FPGA Digital Design

1mo

Senior Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Staff Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Senior Physical Design Engineer

Cirrus Logic Edinburgh, Scotland

ASIC RTL

1mo

Senior Formal Verification Engineer (CH-64001149)

Cirrus Logic Austin, Texas

Verilog System Verilog

1mo

Senior Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior Design Verification Engineer (BO - 01)

Cirrus Logic Chandler, Arizona

VHDL Verilog

1mo

Senior Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Principal SoC Architect (ML Accelerators)

Cirrus Logic Austin, Texas

FPGA ASIC

1mo

Physical Design Engineer (AS-64000921)

Cirrus Logic Austin, Texas

ASIC RTL

1mo

NVM Circuit Design Engineer (MH-US-50021294)

Cirrus Logic Austin, Texas

DFT Design for Test

1mo

NVM Circuit Design Engineer (MH-UK-50021294)

Cirrus Logic Edinburgh, Scotland

DFT Design for Test

1mo

Mixed Signal Modelling and Verification Engineer (#GNEG4)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Embedded Software Engineer (NWB)

Cirrus Logic Newbury, England

FPGA ASIC

1mo

Embedded Software Engineer (LDN)

Cirrus Logic London, England

FPGA ASIC

1mo

Director, Engineering IT Operations

Cirrus Logic Austin, Texas

RTL Place and Route

1mo

Director, Engineering IT Operations

Cirrus Logic Edinburgh, Scotland

RTL Place and Route

1mo

Digital Design Engineer (TR-NWB)

Cirrus Logic Newbury, England

Verilog SystemVerilog

1mo

Digital Design Engineer (AP)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Digital Design Engineer (#OAEG2)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

DFT Engineer (CE-64000920)

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Design Verification Manager

Cirrus Logic Newbury, England

SystemVerilog RTL

1mo

Design Verification Engineer (NWB)

Cirrus Logic Newbury, England

SystemVerilog RTL

1mo

Design Verification Engineer (EDI)

Cirrus Logic Edinburgh, Scotland

SystemVerilog RTL

1mo

Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Analog Mixed Signal Modeling Engineer (UL - 02)

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Analog Design Engineer

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Staff Engineer - CPU Verification

SiFive Hyderabad, Telangana

Verilog SystemVerilog

1mo

Manager / Senior Manager – Design Verification

Silicon Labs Hyderabad, Telangana

SystemVerilog FPGA

1mo

July 29, 2026

Staff/Senior Staff Engineer - AMS Verification

Silicon Labs Hyderabad, Telangana

Verilog System Verilog

2mo

Senior Staff/ Staff Design Engineer

Silicon Labs Singapore, Central Singapore

ASIC RTL

2mo

Senior/Staff Test Engineer

Silicon Labs Singapore, Central Singapore

DFT Design for Test

2mo

Associate Staff CAD Engineer - Physical Verification

Silicon Labs Austin, Texas

SOC Verification

2mo

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

Silicon Labs Austin, Texas

Verilog System Verilog

2mo

Product Test Engineer

Silicon Labs Hsinchu

DFT Design for Test

2mo

Associate Staff/Staff Implementation Design Engineer

Silicon Labs Singapore, Central Singapore

ASIC RTL

2mo

Lead RTL Engineer ( Mixed-Signal IPs)

Silicon Labs Hyderabad, Telangana

Verilog SystemVerilog

2mo

Lead Engineer – IC Design (STA Lead )

Silicon Labs Hyderabad, Telangana

ASIC RTL

2mo

Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)

Silicon Labs Hyderabad, Telangana

ASIC RTL

2mo

Staff Design Engineer - SOC

Silicon Labs Singapore, Central Singapore

RTL Digital Design

2mo

Hardware Designer

Fidus Systems Multiple locations

Remote Verilog FPGA

2mo

July 28, 2026

Sr. Recruiter

Mythic AI Palo Alto, California

RTL Digital Design

2mo