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Cirrus Logic logo
Analog Mixed Signal Modeling Engineer (UL - 02)
Cirrus Logic
Austin , Texas , United States
Verilog SystemVerilog System Verilog
Posted July 30, 2026
SiFive logo
Staff Engineer - CPU Verification
SiFive
Hyderabad , Telangana , India
Verilog SystemVerilog System Verilog
Posted July 30, 2026
Silicon Labs logo
Manager / Senior Manager – Design Verification
Silicon Labs
Hyderabad , Telangana , India
Verilog SystemVerilog FPGA
Posted July 30, 2026
Silicon Labs logo
Staff/Senior Staff Engineer - AMS Verification
Silicon Labs
Hyderabad , Telangana , India
Verilog System Verilog RTL
Posted July 29, 2026
Silicon Labs logo
Senior Staff/ Staff Design Engineer
Silicon Labs
Singapore , Central Singapore , Singapore
ASIC RTL UVM
Posted July 29, 2026
Silicon Labs logo
Sr. Modem Design Verification Engineer
Silicon Labs
Austin , Texas , United States
Verilog SystemVerilog UVM
Posted July 29, 2026
Silicon Labs logo
Associate Staff CAD Engineer - Physical Verification
Silicon Labs
Austin , Texas , United States
Verification
Posted July 29, 2026
Silicon Labs logo
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Silicon Labs
Austin , Texas , United States
Verilog System Verilog RTL
Posted July 29, 2026
Silicon Labs logo
Staff Engineer - IC Design
Silicon Labs
Hyderabad , Telangana , India
Verilog SystemVerilog RTL
Posted July 29, 2026
Silicon Labs logo
Associate Staff/Staff Implementation Design Engineer
Silicon Labs
Singapore , Central Singapore , Singapore
ASIC RTL STA
Posted July 29, 2026
Silicon Labs logo
Lead RTL Engineer ( Mixed-Signal IPs)
Silicon Labs
Hyderabad , Telangana , India
Verilog SystemVerilog RTL
Posted July 29, 2026
Silicon Labs logo
Lead Engineer – IC Design (STA Lead )
Silicon Labs
Hyderabad , Telangana , India
ASIC RTL STA
Posted July 29, 2026
Silicon Labs logo
Senior Engineer – IC Design (Physical Design - PV/Power/EM/IR Drop Engineer)
Silicon Labs
Hyderabad , Telangana , India
ASIC RTL STA
Posted July 29, 2026
Silicon Labs logo
Lead RTL Design Engineer ( Mixed-Signal IPs)
Silicon Labs
Hyderabad , Telangana , India
Verilog SystemVerilog RTL
Posted July 29, 2026
Silicon Labs logo
Staff Design Engineer - SOC
Silicon Labs
Singapore , Central Singapore , Singapore
RTL Verification
Posted July 29, 2026
Fidus Systems logo
Hardware Designer
Fidus Systems
Multiple Locations
Remote! Verilog FPGA ASIC
Posted July 29, 2026
Mythic AI logo
Sr Staff/ Staff Engineer: Physical Design
Mythic AI
Bangalore , Indiana , United States
RTL STA Static Timing
Posted July 28, 2026
Mythic AI logo
Sr Staff /Staff DFT Engineer
Mythic AI
Bangalore , Indiana , United States
Verilog SystemVerilog ASIC
Posted July 28, 2026
Mythic AI logo
Sr DFT Engineer
Mythic AI
Bangalore , Indiana , United States
Verilog SystemVerilog RTL
Posted July 28, 2026
Mythic AI logo
Senior SoC RTL Design Engineer
Mythic AI
Bangalore , Indiana , United States
RTL DFT Design for Test
Posted July 28, 2026
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