UVM Jobs

Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

SystemVerilog ASIC

2mo

Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

SystemVerilog ASIC

2mo

Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

SystemVerilog ASIC

2mo

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Multiple locations

Verilog SystemVerilog

2mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

2mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

2mo

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic Multiple locations

FPGA ASIC

2mo

Staff Engineer, CPU Core Verification

Tenstorrent Bengaluru, Karnataka

RTL UVM

2mo

Sr Staff Engineer, SoC RTL Design

Tenstorrent Toronto, Ontario

VHDL Verilog

2mo

Sr/Staff Engineer, Design Verification,System IP

Tenstorrent Bengaluru, Karnataka

SystemVerilog ASIC

2mo

Sr. Engineer, SoC Design Verification

Tenstorrent Multiple locations

SystemVerilog RTL

2mo

Design Verification Lead, AI Hardware

Tenstorrent Toronto, Ontario

SystemVerilog FPGA

2mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

2mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

2mo

Manager/Director of Hardware Engineering

Baya Systems Santa Clara, California

Verilog SystemVerilog

2mo

Hardware Verification Engineer

Baya Systems Austin, Texas

Verilog SystemVerilog

2mo

Hardware Verification Engineer

Baya Systems Bengaluru, Karnataka

Verilog SystemVerilog

2mo

Hardware Verification Engineer

Baya Systems Cambridge, England

Verilog SystemVerilog

2mo

Hardware Verification Engineer

Baya Systems Santa Clara, California

Verilog SystemVerilog

2mo

Verification Engineer

Fractile London, England

Verilog SystemVerilog

2mo