UVM Jobs in California

AIML enhanced Design/Verification Methodology Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Senior Design Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

GPU Verification Engineer - New College Grad 2026

NVIDIA Multiple locations

FPGA ASIC

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

Senior Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

1mo

Mixed Signal validation engineer

Intel Multiple locations

Verilog System Verilog

1mo

SoC/IP Design Verification Engineer

Intel Multiple locations

SystemVerilog FPGA

1mo

Technical Staff Engineer - Emulation

Microchip Technology Multiple locations

ASIC UVM

1mo

Technical Staff Engineer - Verification

Microchip Technology Multiple locations

Verilog System Verilog

1mo

Senior Verification Engineer - Hardware

NVIDIA Santa Clara, California

VHDL Verilog

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

Senior ASIC Design Engineer - DFX

NVIDIA Santa Clara, California

Verilog ASIC

1mo

Senior Verification Engineer

NVIDIA Santa Clara, California

Verilog SystemVerilog

1mo

Senior Memory Controller Verification Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

ASIC Verification Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

Verilog System Verilog

1mo

ASIC Verification Engineer

NVIDIA Santa Clara, California

SystemVerilog ASIC

1mo