UVM Jobs in California

Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Tenstorrent Multiple locations

SystemVerilog UVM

21d

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

23d

Principal ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

23d

AMS Verification Engineer (RFIC Engineering)

SpaceX Irvine, California

Verilog System Verilog

23d

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

25d

Senior Principal Digital Engineer

Northrop Grumman Woodland Hills, California

VHDL Verilog

26d

Principal ASIC Design Verification Engineer - Terawave

Blue Origin Los Angeles, California

Verilog System Verilog

27d

Principal Modem PHY IP Design Verification Engineer - Terawave

Blue Origin San Diego, California

SystemVerilog FPGA

27d

Senior ASIC Design Verification Engineer - Terawave

Blue Origin Los Angeles, California

Verilog System Verilog

27d

Silicon Validation Engineer

MatX Multiple locations

Remote SystemVerilog RTL

27d

Design Verification Engineer

MatX Multiple locations

Remote SystemVerilog UVM

27d

Emulation Engineer

MatX Multiple locations

Remote Verilog SystemVerilog

27d

SoC Design Verification Engineer

MatX Multiple locations

Remote SystemVerilog UVM

27d

NVIDIA 2027 Internships: Hardware Verification

NVIDIA Santa Clara, California

VHDL Verilog

27d

NVIDIA 2027 Internships: Hardware ASIC Design

NVIDIA Santa Clara, California

VHDL Verilog

27d

Senior ASIC Verification Engineer

NVIDIA Santa Clara, California

ASIC UVM

27d

FPGA Verification Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

SystemVerilog FPGA

27d

R&D Engineer IC Design

Broadcom San Jose, California

Verilog SystemVerilog

1mo

R&D Engineer IC Design

Broadcom San Jose, California

Verilog SystemVerilog

1mo

Design Verification Engineer

Broadcom San Jose, California

Verilog SystemVerilog

1mo