UVM Jobs in California

Senior FPGA Verification Engineer

Anduril Goleta, California

VHDL Verilog

11d

Design Verification Engineer - Compute

MatX Mountain View, California

Remote SystemVerilog UVM

11d

Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

12d

Staff Systems Design Engineer

Analog Devices Multiple locations

SystemVerilog RTL

13d

Sr. Staff Engineer, SoC Design Verification

Tenstorrent Multiple locations

UVM SOC

13d

Senior Firmware Verification and Bringup Engineer

NVIDIA Santa Clara, California

SystemVerilog RTL

14d

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

18d

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

18d

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

18d

Sr. Staff Engineer, CPU (Front-End) Verification

Tenstorrent Multiple locations

SystemVerilog RTL

18d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

19d

Senior Design Verification Engineer - FPGA

BAE Systems Multiple locations

VHDL SystemVerilog

19d

TOP Design Verification Engineer Intern

SK hynix memory solutions America Inc. San Jose, California

Verilog System Verilog

19d

ASICS Design Verification Engineer

Qualcomm San Diego, California

VHDL Verilog

20d

Camera DV Engineer

Qualcomm San Diego, California

Verilog System Verilog

20d

Senior FPGA Verification Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

SystemVerilog FPGA

20d

ASICS Design Verification Engineer-Senior

Qualcomm San Diego, California

VHDL Verilog

21d

Senior Design Verification Engineer - Neuromorphic Computing

Intel Multiple locations

ASIC RTL

21d

Senior Verification Engineer, SoC

NVIDIA Multiple locations

Verilog System Verilog

22d

GPU Design Verification Engineer

Qualcomm Multiple locations

VHDL Verilog

22d