UVM Jobs in California

Staff/Sr. Staff Design Verification

Lightmatter Mountain View, California

SystemVerilog UVM

1mo

ASIC Verification Engineer

Axiado San Jose, California

Verilog System Verilog

1mo

Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)

BAE Systems Multiple locations

VHDL SystemVerilog

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Senior Staff RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Staff Satellite FPGA Engineer (Digital Logic)

E-Space Saratoga, California

VHDL SystemVerilog

1mo

Staff DV Engineer

E-Space Saratoga, California

VHDL Verilog

1mo

SoC Platform Engineer

E-Space Saratoga, California

VHDL SystemVerilog

1mo

Senior DV Engineer

E-Space Saratoga, California

VHDL Verilog

1mo

Principal DV Engineer

E-Space Saratoga, California

VHDL Verilog

1mo

FPGA Verification Engineer - Avionics

E-Space Saratoga, California

SystemVerilog FPGA

1mo

ASIC Verification Engineer

E-Space Saratoga, California

VHDL SystemVerilog

1mo

Verification Engineering Lead/Manager

Omni Design Technologies Milpitas, California

Verilog System Verilog

1mo

Senior RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

Senior Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo