Aug. 30, 2026

SOC Design Verification Engineer

Qualcomm San Diego, California

Verilog System Verilog

17d

CPU Systems RTL Engineer

Qualcomm Multiple locations

VHDL Verilog

17d

CPU Power and Thermal Management Architect

Qualcomm Multiple locations

RTL Logic Design

17d

DDR PHY System Design Engineer (San Diego, US)

Qualcomm San Diego, California

ASIC IP Design

17d

Aug. 29, 2026

Embedded Systems Engineer

CACI San Antonio, Texas

VHDL Verilog

18d

Embedded Systems Engineer

CACI San Antonio, Texas

VHDL Verilog

18d

Senior Field Applications Engineer (FAE)

Microchip Technology Canada - Ontario - Home Office

FPGA RTL

18d

Physical Design Engineer

Broadcom Multiple locations

RTL STA

18d

R&D IC Design Engineer

Broadcom Multiple locations

VHDL Verilog

18d

R&D IC Design Engineer

Broadcom Multiple locations

VHDL Verilog

18d

ASIC Verification Engineer

Broadcom Irvine, California

VHDL Verilog

18d

IP Design Verification Engineer

Intel Bangalore, India

SystemVerilog RTL

18d

SoC Functional Validation Engineer (Temporary position)

Intel Guadalajara, Jalisco

FPGA SOC

18d

Senior Staff Engineer, Physical Design

Marvell Austin, Texas

Verilog ASIC

18d

Principal Engineer, Physical Design

Marvell Austin, Texas

ASIC RTL

18d

Senior Principal Engineer, Physical Design

Marvell Austin, Texas

ASIC RTL

18d

Staff Digital Design Engineer (PCB Design)

Analog Devices Chelmsford, Massachusetts

VHDL Verilog

18d

Embedded Software Architect

Analog Devices Limerick, Ireland

FPGA ASIC

18d

Physical Design Engineer, Sr Staff

Qualcomm Bangalore, India

STA Synthesis

18d

ASIC RTL Design Engineer (Automotive IP/Cores) (Sr. Engr / Sr. Lead Engr)

Qualcomm Bangalore, India

Verilog ASIC

18d

STA Engineer

Qualcomm Hyderabad, Telangana

Verilog FPGA

18d

RTL Design Engineer, Sr Lead

Qualcomm Bangalore, India

Verilog SystemVerilog

18d

Physical Design (Multiple levels)

Qualcomm San Diego, California

ASIC RTL

18d

Principal Ethernet Scale-Out Architect, AI Data Center

Qualcomm Multiple locations

ASIC SOC

18d

Sr. Staff/Principal PCIE Subsystem Architect

Qualcomm Multiple locations

ASIC SOC

18d

CPU EM/IR CAD Engineer (Lead/Staff/Sr Staff)

Qualcomm Multiple locations

FPGA STA

18d

CPU Integration/Physical Verification CAD engineer (Lead/Staff/Sr Staff)

Qualcomm Multiple locations

FPGA Place and Route

18d

CPU STA CAD Engineer (Lead/Staff/Sr Staff)

Qualcomm Multiple locations

FPGA STA

18d

Senior ASIC Verification Engineer, Low Power AI Subsystems

Qualcomm Markham, Ontario

VHDL Verilog

18d

CPU Formal Verification Engineer

Qualcomm Santa Clara, California

Verification

18d

SOC Architect / uArchitect

Qualcomm Bangalore, India

VHDL Verilog

18d

WRD(RTL ) Design - Staff/Manager

Qualcomm Bangalore, India

Verilog System Verilog

18d

SOC Design - Staff

Qualcomm Bangalore, India

FPGA Verification

18d

GPU (RTL) Design - Sr Lead

Qualcomm Bangalore, India

Verilog System Verilog

18d

FPGA Emulation Engineer, up to Staff

Qualcomm Taipei, Taipei

FPGA ASIC

18d

Physical Design Engineer, Sr Lead

Qualcomm Bangalore, India

FPGA RTL

18d

CPU SRAM Design Engineer - Sr Staff / Principal

Qualcomm Austin, Texas

Verilog Static Timing

18d

RTL Design(Peripheral)-Sr Staff

Qualcomm Bangalore, India

FPGA Logic Design

18d

CPU Physical Design Engineer (Senior/Lead)

Qualcomm Hyderabad, Telangana

Verilog FPGA

18d

HW Security Design Engineer

Qualcomm San Diego, California

ASIC Logic Design

18d

ASIC Methodology Engineer

Qualcomm Santa Clara, California

ASIC RTL

18d

System AI Engineer, Display (New Grad Level and up)

Qualcomm Markham, Ontario

ASIC SOC

18d

System Validation Engineer, Senior

Qualcomm Hod HaSharon, Central District

ASIC RTL

18d

Physical Design- Sr Staff Engineer

Qualcomm Chennai, Tamil Nadu

STA Place and Route

18d

Synthesis-DFT Stitch CAD Engineer

Qualcomm San Diego, California

ASIC Place and Route

18d

STA Engineer

Qualcomm Santa Clara, California

ASIC RTL

18d

DFT Engineer, Senior

Qualcomm Toronto, Ontario

FPGA RTL

18d

SoC Design and Integration Engineer

Qualcomm Tijuana, Baja California

FPGA ASIC

18d

Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK

Qualcomm Cambridge, England

ASIC RTL

18d

Server CPU Physical Design Integration Engineer, Staff level - Cambridge, UK

Qualcomm Cambridge, England

ASIC RTL

18d