Aug. 16, 2026

Software Development Engineer(C++,EDA)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Sr Staff QA/Test Eng(RTL, FPGA backend tools)

Lattice Semiconductor Pune, Maharashtra

Verilog FPGA

1mo

Principal Engineer – CAD Design Engineering & EDA Infrastructure

Lattice Semiconductor San Jose, California

FPGA RTL

1mo

Silicon Validation Engineer 3

Lattice Semiconductor San Jose, California

VHDL Verilog

1mo

Silicon Validation Engineer 5

Lattice Semiconductor San Jose, California

VHDL Verilog

1mo

Product Test Engineer

Lattice Semiconductor Hillsboro, Oregon

VHDL Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

SystemVerilog FPGA

1mo

Principal Architecture Engineer

Lattice Semiconductor Pune, Maharashtra

FPGA RTL

1mo

Senior EDA Engineer – RTL Front End Tools & Methodologies

Lattice Semiconductor Pune, Maharashtra

FPGA RTL

1mo

Design Modeling Engineer

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Senior Software Development Engineer(C++, FPGA/EDA)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Silicon Design Validation, Senior Manager

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Sr. Custom Circuit Design Engineer (Memory, FPGA Fabric Designer)

Lattice Semiconductor Pune, Maharashtra

FPGA Verification

1mo

Sr Modeling Design Engineer

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Sr. Staff RTL Eng

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1mo

Sr Staff Software Development Engineer(C++, EDA, Place & Route)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Staff Software Development Engineer(C++, EDA, Place and route)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Sr. Director, Humanoid / Robotics Strategic Marketing

Lattice Semiconductor San Jose, California

FPGA ASIC

1mo

Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

1mo

Staff IP Design Engineer

Lattice Semiconductor Penang, Malaysia

FPGA RTL

1mo

Integration Design Engineer

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

1mo

Senior Soft IP Design Engineer

Lattice Semiconductor Penang, Malaysia

Verilog SystemVerilog

1mo

Staff Applications Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Staff Applications Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Staff Field Applications Engineer

Lattice Semiconductor Taipei, Taipei

VHDL Verilog

1mo

SOC RTL Design Engineer

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1mo

SOC RTL Design Engineer

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1mo

Design Eng 4

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Digital Eng (RTL, implementation)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Field Applications Engineer

Lattice Semiconductor Multiple locations

VHDL Verilog

1mo

Design Eng 2

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Hyderabad, Telangana

SystemVerilog FPGA

1mo

Senior Staff IP Design Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Senior Applications Engineer – FPGA Tools

Lattice Semiconductor LSV

FPGA SOC

1mo

SOC Design Engineer

Lattice Semiconductor Shanghai, Shanghai

Verilog SystemVerilog

1mo

Legal Director, Commercial Transactions – Firmware

Lattice Semiconductor Multiple locations

FPGA SOC

1mo

Staff SW Dev Engineer

Lattice Semiconductor Penang, Malaysia

FPGA RTL

1mo

Aug. 15, 2026

Sr Engineer I - Validation (Systems)

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Principal Engineer - Validation (Systems)

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Technical Staff Engineer - Design

Microchip Technology Burnaby, British Columbia

Verilog System Verilog

1mo

New Graduate Engineer, Silicon Engineering

SpaceX Redmond, Washington

VHDL Verilog

1mo

New Graduate Engineer, Silicon Engineering

SpaceX Palo Alto, California

VHDL Verilog

1mo

New Graduate Engineer, Silicon Engineering

SpaceX Irvine, California

VHDL Verilog

1mo

Electronics Design Engineer

Silvus Technologies Los Angeles, California

FPGA Digital Design

1mo

Mixed Signal Electronic Design Engineer

Draper Cambridge, Massachusetts

VHDL Verilog

1mo

FC Verification Engineer

NVIDIA Yokneam, Israel

SOC Verification

1mo

SOC Verification Engineer

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

ASIC Engineer

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Aug. 14, 2026

Principal Verification Engineer

Microchip Technology Dublin, Leinster

Verilog System Verilog

1mo

FPGA Verification Engineer II

Microchip Technology Dublin, Leinster

Verilog System Verilog

1mo