Latest Posts
Post a Job Join Mailing List I want to be hired!
Apple logo
ASIC Design Engineer - Cache Controller
Apple
Santa Clara , California , United States
RTL SOC
Posted Aug. 1, 2026
Apple logo
CPU Microarchitect/RTL Engineer - Fetch, Out of Order
Apple
Santa Clara , California , United States
RTL Verification
Posted Aug. 1, 2026
Apple logo
C - Focused Design Verification Engineer
Apple
Multiple Locations
Verilog SystemVerilog RTL
Posted Aug. 1, 2026
Tenstorrent logo
Staff Design Verification Engineer, AI HW
Tenstorrent
Multiple Locations
Verilog SystemVerilog RTL
Posted Aug. 1, 2026
Samsung Semiconductor logo
Senior Manager, Technical Marketing, Custom SOC
Samsung Semiconductor
San Jose , California , United States
ASIC
Posted Aug. 1, 2026
Samsung Semiconductor logo
Senior HSIO Digital Design Engineer
Samsung Semiconductor
San Jose , California , United States
Posted Aug. 1, 2026
Virtu Financial logo
2027 Internship- Hardware Engineer (FPGA)
Virtu Financial
Austin , Texas , United States
Verilog SystemVerilog FPGA
Posted Aug. 1, 2026
SpaceX logo
Sr. Electrical Engineer, Hardware Reliability (Starlink)
SpaceX
Bastrop , Texas , United States
FPGA ASIC STA
Posted July 31, 2026
SpaceX logo
Principal DFT Engineer (Silicon Engineering)
SpaceX
Irvine , California , United States
Verilog SystemVerilog ASIC
Posted July 31, 2026
SpaceX logo
Principal DFT Engineer (Silicon Engineering)
SpaceX
Austin , Texas , United States
Verilog SystemVerilog ASIC
Posted July 31, 2026
SpaceX logo
Principal DFT Engineer (Silicon Engineering)
SpaceX
Palo Alto , California , United States
Verilog SystemVerilog ASIC
Posted July 31, 2026
SK hynix memory solutions America Inc. logo
Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
SK hynix memory solutions America Inc.
San Jose , California , United States
Verilog SystemVerilog ASIC
Posted July 31, 2026
SK hynix memory solutions America Inc. logo
ASIC Design Engineer
SK hynix memory solutions America Inc.
San Jose , California , United States
Verilog SystemVerilog RTL
Posted July 31, 2026
Tenstorrent logo
Design Verification Engineer, Automotive Robotics
Tenstorrent
Munich , Bavaria , Germany
Verilog SystemVerilog UVM
Posted July 31, 2026
Cirrus Logic logo
System Emulation and Evaluation Engineer
Cirrus Logic
Edinburgh , Scotland
FPGA ASIC RTL
Posted July 30, 2026
Cirrus Logic logo
System Emulation and Evaluation Engineer
Cirrus Logic
Newbury , England , United Kingdom
FPGA ASIC RTL
Posted July 30, 2026
Cirrus Logic logo
Staff Digital Design Engineer
Cirrus Logic
Austin , Texas , United States
Verilog ASIC RTL
Posted July 30, 2026
Cirrus Logic logo
Staff Design Verification Engineer
Cirrus Logic
Austin , Texas , United States
VHDL Verilog SystemVerilog
Posted July 30, 2026
Cirrus Logic logo
Senior Staff Digital Design Engineer
Cirrus Logic
Austin , Texas , United States
Verilog ASIC RTL
Posted July 30, 2026
Cirrus Logic logo
Senior Staff Design Verification Engineer
Cirrus Logic
Austin , Texas , United States
VHDL Verilog SystemVerilog
Posted July 30, 2026
See prior page
Show me more