Aug. 5, 2026

Staff System Validation Engineer

SiFive Hsinchu, Hsinchu

FPGA Chisel

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Senior Staff RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Product Power Engineer

SiFive Multiple locations

FPGA ASIC

1mo

Power Model Engineer

SiFive Multiple locations

FPGA ASIC

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Core Performance Architect

SiFive Multiple locations

FPGA RTL

1mo

Aug. 4, 2026

Zebu flow Engineer

SiFive Bengaluru, Karnataka

Verilog FPGA

1mo

Senior FPGA Engineer (VHDL/Verilog)

AGAD Technology Schelle, Flanders, Belgium

VHDL Verilog

1mo

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

Verilog SystemVerilog

1mo

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

ASIC RTL

1mo

Summer 2027 Silicon Engineering Internship/Co-op

SpaceX Flexible - Any SpaceX Site

VHDL Verilog

1mo

Sr. PCB Designer (Starlink)

SpaceX Bastrop, Texas

FPGA Digital Design

1mo

Spring 2027 Silicon Engineering Internship/Co-op

SpaceX Flexible - Any SpaceX Site

VHDL Verilog

1mo

Hardware Engineer (FPGA/ASIC)

Jane Street London, England

VHDL Verilog

1mo

Hardware Engineer (FPGA/ASIC)

Jane Street London, England

VHDL Verilog

1mo

Aug. 2, 2026

Intern - Design Verification Infrastructure Engineer - Platform

SiFive Multiple locations

Chisel Verification

1mo

Aug. 1, 2026

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Processor Performance Verification Engineer

Apple Santa Clara, California

Verilog System Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

RFIC Design Engineer

Apple Multiple Locations

RTL SOC

1mo

RFIC Layout Engineer

Apple Multiple Locations

RTL SOC

1mo

RFIC Layout Engineer

Apple Multiple Locations

RTL SOC

1mo

CPU Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

RTL Design Engineer

Apple San Diego, California

RTL Verification

1mo

RTL Design Engineer

Apple Cupertino, California

RTL Verification

1mo

RTL Design Engineer

Apple Melbourne, United States

RTL Verification

1mo

RTL Design Engineer

Apple Austin, Texas

RTL Verification

1mo

RTL Design Engineer

Apple Beaverton, United States

RTL Verification

1mo

RTL Design Engineer

Apple Waltham, Massachusetts

RTL Verification

1mo

Wireless Design Verification Engineer

Apple Multiple Locations

RTL SOC

1mo

PHY Design Verification Engineer

Apple Multiple Locations

RTL SOC

1mo

Wireless SOC FW Engineer

Apple Multiple Locations

RTL SOC

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU ML Microarchitect/RTL Engineer

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Multiple Locations

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Execution, Load/Store

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Microarchitect/RTL Engineer - Fetch, Out of Order

Apple Santa Clara, California

VHDL Verilog

1mo

CPU Power Management Microarchitect/RTL Engineer

Apple Multiple Locations

VHDL Verilog

1mo

CPU Cache Microarchitect/RTL Engineer

Apple Multiple Locations

VHDL Verilog

1mo