UVM Jobs

Digital Verification Engineer

Neuralink South San Francisco, California, United States

SystemVerilog FPGA

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

1mo

Senior Staff RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

1mo

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

1mo

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

1mo

Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Staff Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior Staff Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Senior Formal Verification Engineer (CH-64001149)

Cirrus Logic Austin, Texas

Verilog System Verilog

1mo

Senior Digital Design Engineer (#OAEG3)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Senior Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Senior Design Verification Engineer (BO - 01)

Cirrus Logic Chandler, Arizona

VHDL Verilog

1mo

Senior Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo