UVM Jobs

Mixed Signal Modelling and Verification Engineer (#GNEG4)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Digital Design Engineer (TR-NWB)

Cirrus Logic Newbury, England

Verilog SystemVerilog

1mo

Digital Design Engineer (AP)

Cirrus Logic Edinburgh, Scotland

Verilog SystemVerilog

1mo

Digital Design Engineer

Cirrus Logic Austin, Texas

Verilog ASIC

1mo

Design Verification Manager

Cirrus Logic Newbury, England

SystemVerilog RTL

1mo

Design Verification Engineer (NWB)

Cirrus Logic Newbury, England

SystemVerilog RTL

1mo

Design Verification Engineer (EDI)

Cirrus Logic Edinburgh, Scotland

SystemVerilog RTL

1mo

Design Verification Engineer

Cirrus Logic Austin, Texas

VHDL Verilog

1mo

Analog Mixed Signal Modeling Engineer (UL - 02)

Cirrus Logic Austin, Texas

Verilog SystemVerilog

1mo

Staff Engineer - CPU Verification

SiFive Hyderabad, Telangana

Verilog SystemVerilog

1mo

Manager / Senior Manager – Design Verification

Silicon Labs Hyderabad, Telangana

SystemVerilog FPGA

1mo

Staff/Senior Staff Engineer - AMS Verification

Silicon Labs Hyderabad, Telangana

Verilog System Verilog

1mo

Senior Staff/ Staff Design Engineer

Silicon Labs Singapore, Central Singapore

ASIC RTL

1mo

Senior Digital Verification Engineer

Mythic AI Bangalore, Indiana

Verilog SystemVerilog

1mo

Senior Design Verification Engineer

Mythic AI Austin, Texas

Verilog SystemVerilog

1mo

Design Verification Engineer

Mythic AI Austin, Texas

Verilog SystemVerilog

1mo

Staff Satellite FPGA Engineer (Digital Logic)

E-Space Saratoga, California

VHDL SystemVerilog

1mo

Staff DV Engineer

E-Space Saratoga, California

VHDL Verilog

1mo

SoC Platform Engineer

E-Space Saratoga, California

VHDL SystemVerilog

1mo

Senior DV Engineer

E-Space Saratoga, California

VHDL Verilog

1mo